The JAM CPU core

The JAM CPU is a 32bit 5 stage pipelined RISC core with forwarding and hazard handling. Its basic design is derived from the DLX architecture (from the Patterson & Hennessy books). The JAM CPU core is implemented in VHDL and has been tested in an actual FPGA (the Xilinx Virtex I chip).

We have released our CPU core under the GNU Lesser General Public License (LGPL) in the hope that it will be useful for people studying VHDL or computer architecture.

Download the JAM CPU core!

The JAM CPU core is copyrighted (C) 2002 by
Anders Lindström, Johan E. Thelin and Michael Nordseth.

You can mail me (Anders Lindström) at cal[at]swipnet[dot]se (replace [at] with @ and [dot] with .).

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